On Wed, Apr 12, 2023 at 09:14:59AM +0200, Roman Beranek wrote: > On Wed Apr 5, 2023 at 5:03 PM CEST, Maxime Ripard wrote: > > On Wed, Apr 05, 2023 at 02:34:11PM +0200, Roman Beranek wrote: > > > It turns out however that the new dclk rates can't be set exactly as > > > requested without touching pll-video0*, tcon0 now therefore gets > > > reparented from pll-mipi to pll-video0-2x which, as it further turns > > > out, breaks DSI. While simply forbidding the video0-2x mux option seems > > > to me as the right way to go because there's not much use for it with > > > non-DSI interfaces either besides the opportunity to power pll-mipi > > > down, I'd like to run by you first. > > > > Sounds reasonable > > Okay, I'm unsure of how to denote that in the code however. Should I > just comment the parent out of the table and put an explanation in > a comment nearby? Or just erase it? I couldn't find an applicable > precedent. I think that forcing the parent at boot, and adding the CLK_SET_RATE_NOREPARENT flag should be enough. > > > * As pll-mipi doesn't have CLK_SET_RATE_PARENT flag set, pll-video0 > > > retains its boot-time rate of 294 MHz set by sunxi-dw-hdmi driver > > > in u-boot. Why 294 MHz (as opposed to the default rate of 297 MHz)? > > > The driver actually asks for 297 MHz, clock_set_pll3 rounds it to > > > 294 MHz though because it limits itself to 6 MHz steps. > > > > We could also address that though > > Should I include it in v2 of the series, or leave it for later? I guess you can include it into this one too Maxime
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