Hello Maxime, On Wed Mar 29, 2023 at 9:58 PM CEST, Maxime Ripard wrote: > > In order to preserve semantic correctness however, I propose to preface > > the change with a patch that renames sun4i_dotclock and tcon-pixel-clock > > such that dot/pixel is replaced with d/data. What do you think? > > I don't think it's exposed to the userspace in any way so it makes sense to me > Here's a new series that includes those renames: <https://lore.kernel.org/all/20230331110245.43527-1-me@xxxxxxx/> It turns out however that the new dclk rates can't be set exactly as requested without touching pll-video0*, tcon0 now therefore gets reparented from pll-mipi to pll-video0-2x which, as it further turns out, breaks DSI. While simply forbidding the video0-2x mux option seems to me as the right way to go because there's not much use for it with non-DSI interfaces either besides the opportunity to power pll-mipi down, I'd like to run by you first. Kind regards, Roman * As pll-mipi doesn't have CLK_SET_RATE_PARENT flag set, pll-video0 retains its boot-time rate of 294 MHz set by sunxi-dw-hdmi driver in u-boot. Why 294 MHz (as opposed to the default rate of 297 MHz)? The driver actually asks for 297 MHz, clock_set_pll3 rounds it to 294 MHz though because it limits itself to 6 MHz steps.
