On Mon, Mar 06, 2023 at 12:49:52PM -0800, Lucas De Marchi wrote: > dg1_gt_workarounds_init() is only ever called for DG1, so there is no > point checking it again. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 32aa1647721a..eb6cc4867d67 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1472,21 +1472,15 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > static void > dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > { > - struct drm_i915_private *i915 = gt->i915; > - Looks like you pushed some stale version of this patch which didn't remove this variable. Now the CONFIG_DRM_I915_WERROR=y build is broken. Did you lose that from your pre-push build .config? > gen12_gt_workarounds_init(gt, wal); > > /* Wa_1409420604:dg1 */ > - if (IS_DG1(i915)) > - wa_mcr_write_or(wal, > - SUBSLICE_UNIT_LEVEL_CLKGATE2, > - CPSSUNIT_CLKGATE_DIS); > + wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, > + CPSSUNIT_CLKGATE_DIS); > > /* Wa_1408615072:dg1 */ > /* Empirical testing shows this register is unaffected by engine reset. */ > - if (IS_DG1(i915)) > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > - VSUNIT_CLKGATE_DIS_TGL); > + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); > } > > static void > -- > 2.39.0 -- Ville Syrjälä Intel