Hi, On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote: > Having a bigger number of FIFO lines held after vsync is only useful to > SoCs using AFBC to give time to the AFBC decoder to be reset, configured > and enabled again. > > For SoCs not using AFBC this, on the contrary, is causing on some > displays issues and a few pixels vertical offset in the displayed image. > > [...] Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes) [1/1] drm/meson: Reduce the FIFO lines held when AFBC is not used https://cgit.freedesktop.org/drm/drm-misc/commit/?id=3b754ed6d1cd90017e66e5cc16f3923e4a952ffc -- Neil
