On 19/12/2022 12:00, Martin Blumenstingl wrote:
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@xxxxxxxxxxxx> wrote:
Having a bigger number of FIFO lines held after vsync is only useful to
SoCs using AFBC to give time to the AFBC decoder to be reset, configured
and enabled again.
For SoCs not using AFBC this, on the contrary, is causing on some
displays issues and a few pixels vertical offset in the displayed image.
On the 32-bit SoCs (for which VPU support is not upstream yet) it has
caused screen tearing instead of shifting the image.
Conditionally increase the number of lines held after vsync only for
SoCs using AFBC, leaving the default value for all the others.
That was also my approach (for a not-yet-upstream patch).
Since it's affecting already supported SoCs I suggest adding
"Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
is applying the patch).
Acked-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
Yep I'll add the Fixes tag when applying
Thank Carlo !
Acked-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
