It takes some time until the enable GPIO has settled when turning on.
This delay is platform specific and may be caused by e.g. voltage shifts,
capacitors etc.
Fall back to current default if not specified in DT.
Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
index 047c14ddbbf11..6510ee384315e 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
@@ -145,6 +145,7 @@ struct sn65dsi83 {
struct drm_bridge *panel_bridge;
struct gpio_desc *enable_gpio;
struct regulator *vcc;
+ u32 enable_delay;
bool lvds_dual_link;
bool lvds_dual_link_even_odd_swap;
};
@@ -346,7 +347,7 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
/* Deassert reset */
gpiod_set_value_cansleep(ctx->enable_gpio, 1);
- usleep_range(10000, 11000);
+ fsleep(ctx->enable_delay);
/* Get the LVDS format from the bridge state. */
bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
@@ -603,6 +604,10 @@ static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
return dev_err_probe(dev, PTR_ERR(ctx->vcc),
"Failed to get supply 'vcc'\n");
+ if (of_property_read_u32(dev->of_node, "ti,enable-delay-us",
+ &ctx->enable_delay))
+ ctx->enable_delay = 10000;
+
return 0;
}
--
2.34.1
