In case the downstream bridge state reports DSI HS clock minimum and
maximum limits, find the most suitable DSI HS clock rate and use it
for the DSI link.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Laurent Pinchart <Laurent.pinchart@xxxxxxxxxxxxxxxx>
Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Cc: Maxime Ripard <maxime@xxxxxxxxxx>
Cc: Robert Foss <robert.foss@xxxxxxxxxx>
Cc: Sam Ravnborg <sam@xxxxxxxxxxxx>
---
drivers/gpu/drm/bridge/samsung-dsim.c | 34 +++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 9623923036292..697329d0faa35 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1399,7 +1399,41 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);
struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+ struct drm_bridge *next_bridge = drm_bridge_get_next_bridge(bridge);
+ struct drm_bridge_state *next_bridge_state;
+ /* This DSIM bridge can produce HS clock in range of 12..750 MHz */
+ bridge_state->hs_rate_min = 12000;
+ bridge_state->hs_rate_max = 750000;
+
+ if (next_bridge) {
+ next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,
+ next_bridge);
+ /*
+ * This bridge ability to provide HS clock does not overlap
+ * with next bridge HS clock requirements, link constraints
+ * are not met and link can not be operational.
+ */
+ if (bridge_state->hs_rate_max < next_bridge_state->hs_rate_min ||
+ bridge_state->hs_rate_min > next_bridge_state->hs_rate_max)
+ goto exit;
+
+ /*
+ * In case the nearest bridge specifies DSI HS clock rate
+ * and supports DSI burst mode, run the DSI link at highest
+ * supported DSI HS clock frequency to achieve the shortest
+ * transfer bursts, longest time in LP mode between bursts,
+ * and thus most power efficient transfer.
+ *
+ * Note that DSI HS clock lane frequency is
+ * DSIM PLL output / 2 .
+ */
+ dsi->burst_clk_rate = min(bridge_state->hs_rate_max,
+ next_bridge_state->hs_rate_max) *
+ 2 * 1000;
+ }
+
+exit:
/*
* The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
* inverts HS/VS/DE sync signals polarity, therefore, while
--
2.35.1
