In case TC358767 operates in DSI-to-DPI mode and its clock are supplied
from XTal connected to RefClk, the range of supported input DSI HS clock
is limited.
Expose this limitation to the upstream bridge by providing minimum and
maximum accepted DSI HS clock frequency via bridge state.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Laurent Pinchart <Laurent.pinchart@xxxxxxxxxxxxxxxx>
Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Cc: Maxime Ripard <maxime@xxxxxxxxxx>
Cc: Robert Foss <robert.foss@xxxxxxxxxx>
Cc: Sam Ravnborg <sam@xxxxxxxxxxxx>
---
drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index b5f4e5328eaf9..3f423a29c703b 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1516,10 +1516,34 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
+ struct tc_data *tc = bridge_to_tc(bridge);
+ unsigned int dpi_max_pixrate;
+
/* DSI->DPI interface clock limitation: upto 100 MHz */
if (crtc_state->adjusted_mode.clock > 100000)
return -EINVAL;
+ bridge_state->hs_rate_min =
+ crtc_state->adjusted_mode.clock *
+ mipi_dsi_pixel_format_to_bpp(tc->dsi->format);
+ /* Split video data transfer across multiple lanes */
+ bridge_state->hs_rate_min /= tc->dsi->lanes;
+ /* DSI bus is DDR */
+ bridge_state->hs_rate_min /= 2;
+ /* Apply 1.2 DSI protocol overhead */
+ bridge_state->hs_rate_min =
+ bridge_state->hs_rate_min * 12 / 10;
+
+ /*
+ * The bridge supports maximum DPI resolution 1366x768 24bpp 60Hz
+ * and is not capable of running at full 500 MHz in all data lane
+ * configurations at least in DSI-to-DPI mode.
+ */
+ dpi_max_pixrate = 1366 * 768 * 24 * 60 / 1000;
+ bridge_state->hs_rate_max =
+ clamp((dpi_max_pixrate * 12 / 10) / tc->dsi->lanes / 2,
+ 0U, 500000U);
+
return 0;
}
--
2.35.1
