On 1.10.2022 21:08, Marijn Suijten wrote: > drm_dsc_config's bits_per_pixel field holds a fractional value with 4 > bits, which all panel drivers should adhere to for > drm_dsc_pps_payload_pack() to generate a valid payload. All code in the > DSI driver here seems to assume that this field doesn't contain any > fractional bits, hence resulting in the wrong values being computed. > Since none of the calculations leave any room for fractional bits or > seem to indicate any possible area of support, disallow such values > altogether. > > Fixes: b9080324d6ca ("drm/msm/dsi: add support for dsc data") > Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx> Konrad > drivers/gpu/drm/msm/dsi/dsi_host.c | 34 +++++++++++++++++++++++------- > 1 file changed, 26 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index cb6f2fa11f58..42a5c9776f52 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -847,6 +847,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > u32 pkt_per_line; > u32 bytes_in_slice; > u32 eol_byte_num; > + int bpp = dsc->bits_per_pixel >> 4; > + > + if (dsc->bits_per_pixel & 0xf) > + /* dsi_populate_dsc_params() already caught this case */ > + pr_err("DSI does not support fractional bits_per_pixel\n"); > > /* first calculate dsc parameters and then program > * compress mode registers > @@ -860,7 +865,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > if (slice_per_intf > dsc->slice_count) > dsc->slice_count = 1; > > - bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8); > + bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * bpp, 8); > > dsc->slice_chunk_size = bytes_in_slice; > > @@ -913,6 +918,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) > u32 va_end = va_start + mode->vdisplay; > u32 hdisplay = mode->hdisplay; > u32 wc; > + int ret; > > DBG(""); > > @@ -948,7 +954,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) > /* we do the calculations for dsc parameters here so that > * panel can use these parameters > */ > - dsi_populate_dsc_params(dsc); > + ret = dsi_populate_dsc_params(dsc); > + if (ret) > + return; > > /* Divide the display by 3 but keep back/font porch and > * pulse width same > @@ -1229,6 +1237,10 @@ static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, > if (packet.size < len) > memset(data + packet.size, 0xff, len - packet.size); > > + if (msg->type == MIPI_DSI_PICTURE_PARAMETER_SET) > + print_hex_dump(KERN_DEBUG, "ALL:", DUMP_PREFIX_NONE, > + 16, 1, data, len, false); > + > if (cfg_hnd->ops->tx_buf_put) > cfg_hnd->ops->tx_buf_put(msm_host); > > @@ -1786,6 +1798,12 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc) > int data; > int final_value, final_scale; > int i; > + int bpp = dsc->bits_per_pixel >> 4; > + > + if (dsc->bits_per_pixel & 0xf) { > + pr_err("DSI does not support fractional bits_per_pixel\n"); > + return -EINVAL; > + } > > dsc->rc_model_size = 8192; > dsc->first_line_bpg_offset = 12; > @@ -1807,7 +1825,7 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc) > } > > dsc->initial_offset = 6144; /* Not bpp 12 */ > - if (dsc->bits_per_pixel != 8) > + if (bpp != 8) > dsc->initial_offset = 2048; /* bpp = 12 */ > > mux_words_size = 48; /* bpc == 8/10 */ > @@ -1830,16 +1848,16 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc) > * params are calculated > */ > groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3); > - dsc->slice_chunk_size = dsc->slice_width * dsc->bits_per_pixel / 8; > - if ((dsc->slice_width * dsc->bits_per_pixel) % 8) > + dsc->slice_chunk_size = dsc->slice_width * bpp / 8; > + if ((dsc->slice_width * bpp) % 8) > dsc->slice_chunk_size++; > > /* rbs-min */ > min_rate_buffer_size = dsc->rc_model_size - dsc->initial_offset + > - dsc->initial_xmit_delay * dsc->bits_per_pixel + > + dsc->initial_xmit_delay * bpp + > groups_per_line * dsc->first_line_bpg_offset; > > - hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->bits_per_pixel); > + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, bpp); > > dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay; > > @@ -1862,7 +1880,7 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc) > data = 2048 * (dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits); > dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total); > > - target_bpp_x16 = dsc->bits_per_pixel * 16; > + target_bpp_x16 = bpp * 16; > > data = (dsc->initial_xmit_delay * target_bpp_x16) / 16; > final_value = dsc->rc_model_size - data + num_extra_mux_bits;