Hi Dave, Adam,
On 22-08-03, Dave Stevenson wrote:
> Hi Adam
>
> On Wed, 3 Aug 2022 at 12:03, Adam Ford <aford173@xxxxxxxxx> wrote:
...
> > > Did managed to get access to the ADV7535 programming guide? This is the
> > > black box here. Let me check if I can provide you a link with our repo
> > > so you can test our current DSIM state if you want.
> >
> > I do have access to the programming guide, but it's under NDA, but
> > I'll try to answer questions if I can.
>
> Not meaning to butt in, but I have datasheets for ADV7533 and 7535
> from previously looking at these chips.
Thanks for stepping into :)
> Mine fairly plainly states:
> "The DSI receiver input supports DSI video mode operation only, and
> specifically, only supports nonburst mode with sync pulses".
I've read this also, and we are working in nonburst mode with sync
pulses. I have no access to an MIPI-DSI analyzer therefore I can't
verify it.
> Non-burst mode meaning that the DSI pixel rate MUST be the same as the
> HDMI pixel rate.
On DSI side you don't have a pixel-clock instead there is bit-clock.
> Section 6.1.1 "DSI Input Modes" of adv7533_hardware_user_s_guide is
> even more explicit about the requirement of DSI timing matching
Is it possible to share the key points of the requirements?
> The NXP kernel switching down to an hs_clk of 445.5MHz would therefore
> be correct for 720p operation.
It should be absolute no difference if you work on 891MHz with 2 lanes
or on 445.5 MHz with 4 lanes. What must be ensured is that you need the
minimum required bandwidth which is roughly: 1280*720*24*60 = 1.327
GBps.
> If you do program the manual DSI divider register to allow a DSI pixel
> rate of 148.5MHz vs HDMI pixel rate of 74.25MHz, you'd be relying on
There is no such DSI pixel rate to be precise, we only have a DSI bit
clock/rate.
> the ADV753x having at least a half-line FIFO between DSI rx and HDMI
> tx to compensate for the differing data rates. I see no reference to
> such, and I'd be surprised if it was more than a half dozen pixels to
> compensate for the jitter in the cases where the internal timing
> generator is mandatory due to fractional bytes.
This is interesting and would proofs our assumption that the device
don't have a FIFO :)
Our assumptions (we don't have the datasheet/programming manual):
- HDMI part is fetching 3 bytes per HDMI pixclk
- Ratio between dsi-clk and hdmi-pixelclk must be 3 so the DSI and
HDMI are in sync. So from bandwidth pov there are no differences
between:
- HDMI: 74.25 MHz * 24 Bit = 1782.0 MBit/s
- DSI: 891 MHz * 2 lanes = 1782.0 MBit/s (dsi-clock: 445.5 )
- DSI: 445.5 MHz * 4 lanes = 1782.0 MBit/s (dsi-clock: 222.75)
But the ratio is different and therefore the faster clocking option
let something 'overflow'.
Anyway, but all this means that Adam should configure the
burst-clock-rate to 445.5 and set the lanes to 4. But this doesn't work
either and now we are back on my initial statement -> the driver needs
some attention.
Regards,
Marco
