On Tue, Aug 2, 2022 at 8:51 AM Adam Ford <aford173@xxxxxxxxx> wrote: > > On Tue, Aug 2, 2022 at 7:13 AM Adam Ford <aford173@xxxxxxxxx> wrote: > > > > On Tue, Aug 2, 2022 at 3:08 AM Marco Felsch <m.felsch@xxxxxxxxxxxxxx> wrote: > > > > > > Hi Adam, Fabio, > > > > > > On 22-08-01, Adam Ford wrote: > > > > On Mon, Aug 1, 2022 at 8:53 PM Fabio Estevam <festevam@xxxxxxxxx> wrote: > > > > > > > > > > On Mon, Aug 1, 2022 at 10:39 PM Adam Ford <aford173@xxxxxxxxx> wrote: > > > > > > > > > > > I managed to get my HDMI output working. I had the lanes set to 2 > > > > > > instead of 4. Once I switched to 4-lanes, the monitor came up in > > > > > > 1080p. I haven't yet been able to get other modes to work. > > > > > > > > > > Ok, good. On another thread, you mentioned that you were also trying > > > > > to get LVDS to work via SN65DSI83. > > > > > > > > > > Does LVDS work for you on this branch? > > > > > > > > I haven't tried with Marek's latest suggestion. In the other thread > > > > he mentioned a burst mode and setting the DSI speeds to higher > > > > frequencies, but the patch he had didn't look like it would apply > > > > cleanly, so I will need to dig into that a bit further. > > > > > > Can you provide me a link to this thread? > > > > Sure, > > > > https://www.spinics.net/lists/dri-devel/msg358301.html > > > > > > > > > Since my company doesn't really ship the LVDS displays with the kits, > > > > the HDMI is the default video, so I've been focusing on it. > > > > > > > > To answer Marco's question, I was able to revert "MLK-21958-13: > > > > drm/bridge: adv7511: Limit supported clocks" and still get a display > > > > at 1080p, but all the other resolutions I tried appear to come up > > > > blank. > > > > > > Cool so now you have the same state as we are. > > > > I have a couple patches applied to mine which mimic some of the stuff > > that NXP did. Since I have access to a programmer manual, i was able > > to confirm some of the 7535 specific stuff and the low-refresh rate > > changes in their kernel appear appropriate and I also created a second > > table of default settings for the 7535 and if the type is set > > properly, i'll use the newer table instead of the older one. If anyone > > wants any of these patches, I can certainly share them, but I am not > > certain they make any difference. > > > > There are a few other items in the programmer manual that I want to > > attempt to implement once I have a chance to further review the > > document. > > > > > > > > I think that the most important one is the blanking calc. Can you try to > > > revert "drm/bridge: adv7511: Repair bus_flags and bus_format" and check > > > if you can get a output still? Also something to try would be to disable > > > the internal timing generator by specifying > > > 'adi,disable-timing-generator'. Also if you have an oscilloscope for > > I did some reading about the internal timing generator. It appears > that it's required when video formats use fractional bytes, and it's > preconfigured to run at 720p by default, but registers 28h through 37h > configure it for other video modes. I think there may still be some issues with the DSIM since some of the clock frequencies are set in the device tree. >From what I can tell, the pixel rate is calculated based on the burst-clock-frequency and that generates a byte clock. For 891000000, the byte clock is 111375000. Modetest timings for 1080p show: index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot #0 1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: nhsync, nvsync; type: driver When looking at modetest, there is a clock for 1080p which appears to be 148500. 111375000/148500 = 750. The rest of the entries in my table do not divide evenly. I don;t know if that explains the lack of display, but it's something to note. It seems to me that instead of fixing the samsung,burst-clock-frequency to 891000000, we should make the desired PLL related to the desired pixel clock so it divides evenly. Looking at NXP's kernel, I also noticed that their esc_prescaler is based on the byte clock divided by 20MHz. With some small code changes to get the PLL based on the desired pixel clock instead of hard-coded, I was able to set samsung,burst-clock-frequency = <1500000000>; samsung,esc-clock-frequency = <20000000>; With these settings and the above mentioned code changes, 1080p still appears, however when attempting other modes, the display still fails to load. I also noticed that the phy ref clock is set to 27MHz instead of NXP's 12MHz. I attempted to play with that setting, but I couldn't get 1080p to work again, so I backed it out. Maybe I am headed in the wrong direction, but I'm going to examine the P/M/S calculation of the timing on NXP's kernel to see how the DSIM in this code compares. If someone who understands the interactions between these different components has suggestions, I'm willing to run some experiments. adam > > Are you thinking the imx8mm DSI generator would do it better? > > > > such frequencies you can check the hdmi clk-lane. I noticed that this is > > > sometimes wrong. > > > > I am doing this from my home office as a side project, so I don't have > > a scope, but I can try to revert the other patch and try to disable > > the internal timing generator when I get home tonight. I'll report my > > findings. > > > > > > > > Regards, > > > Marco > > > > > > > I didn't try every one. With that revert, more options come > > > > available, but 1440x900 and 800x600 were options I tried > > > > unsuccessfullyl. > > > > > > > > > > > adam > > > >
