Re: [PATCH 2/3] drm/bridge: tc358767: increase CLRSIPO count

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On 7/6/22 15:28, Lucas Stach wrote:
The current CLRSIPO count is marginal and does not work with high
DSI clock rates. Increase it a bit to allow the DSI link to work at
up to 1Gbps lane speed.

Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>

Reviewed-by: Marek Vasut <marex@xxxxxxx>
Tested-by: Marek Vasut <marex@xxxxxxx>



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