Hi, Bo-Chen:
On Mon, 2022-06-27 at 16:03 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
>
> This patch adds a embedded displayport driver for the MediaTek mt8195
> SoC.
>
> It supports the MT8195, the embedded DisplayPort units. It offers
> DisplayPort 1.4 with up to 4 lanes.
>
> The driver creates a child device for the phy. The child device will
> never exist without the parent being active. As they are sharing a
> register range, the parent passes a regmap pointer to the child so
> that
> both can work with the same register range. The phy driver sets
> device
> data that is read by the parent to get the phy device that can be
> used
> to control the phy properties.
>
> This driver is based on an initial version by
> Jitao shi <jitao.shi@xxxxxxxxxxxx>
>
> Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx>
> [Bo-Chen: Cleanup the drivers and modify comments from reviewers]
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx>
> ---
[snip]
> +
> +static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
> +{
> + u32 sram_read_start = MTK_DP_TBC_BUF_READ_START_ADDR;
This initial value is redundant. So remove this initial value.
> +
> + if (mtk_dp->train_info.lane_count > 0) {
This checking would always be true.
This function would be called after training success, so mtk_dp-
>train_info.lane_count would be greater than 0.
So remove this checking.
Regards,
CK
> + sram_read_start = min_t(u32,
> + MTK_DP_TBC_BUF_READ_START_ADDR,
> + mtk_dp->info.timings.vm.hactive
> /
> + mtk_dp->train_info.lane_count /
> + MTK_DP_4P1T / MTK_DP_HDE /
> MTK_DP_PIX_PER_ADDR);
> + mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);
> + }
> +
> + mtk_dp_setup_encoder(mtk_dp);
> +}
> +
