Hi Marek. On Tue, 5 Apr 2022 at 14:49, Marek Vasut <marex@xxxxxxx> wrote: > > On 4/5/22 15:25, Dave Stevenson wrote: > > On Tue, 5 Apr 2022 at 14:08, Laurent Pinchart > > <laurent.pinchart@xxxxxxxxxxxxxxxx> wrote: > >> > >> Hi Dave, > >> > >> On Tue, Apr 05, 2022 at 01:00:28PM +0100, Dave Stevenson wrote: > >>> On Tue, 5 Apr 2022 at 12:42, Laurent Pinchart wrote: > >>>> On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote: > >>>>> In rare cases, the bridge may not start up correctly, which usually > >>>>> leads to no display output. In case this happens, warn about it in > >>>>> the kernel log. > >>>> > >>>> Do you know what this is caused by ? It's a bit annoying to add a 10+ms > >>>> delay at start time just to be notified of rare cases. > >>> > >>> The datasheet [1] section 7.4.2 Initialization Sequence states in step 2 > >>> "After power is applied and stable, the DSI CLK lanes MUST be in HS > >>> state and the DSI data lanes MUST be driven > >>> to LP11 state" > >>> Data lanes shouldn't go to HS until step 8 after the DSI83 has been configured. > >>> > >>> Configuration from the driver is being done from atomic_enable, > >>> therefore the data lanes are likely in HS mode and sending video, not > >>> LP11. > >>> > >>> Deviate from the specified initialisation sequence at your peril! > >>> > >>> The SN65DSI8[3|4|5] is one of the DSI devices that I'd been looking at > >>> with the DSI ordering patches [2] so that we could initialise it in > >>> the way specified in the datasheet. I've had no responses to v2 of > >>> those patches though. > >> > >> Sounds like I need to review that :-) It's still in my queue, I'll try > >> to push it to the top. > >> > >> Do you think this patch could then be reverted ? > > > > If we can initialise the DSI host before the bridge for the > > pre_enable, then all the configuration moves to the atomic_pre_enable > > and there should be no need to have the delay. > > > > I can't 100% guarantee that, but one of the folks on the Pi forums is > > using [1] which does that, and is reporting it working well. (He's > > also using the DSI85 to take 2 DSI links and drive 2 LVDS single link > > panels) > > It seems to me that checking whether the bridge got correctly > initialized is orthogonal to the aforementioned patchset though ? It's the delay that is ugly. Put the check in atomic_enable which will be slightly later than configuration in pre_enable? Check that sufficient jiffies have passed if you needed. Or wire up the IRQ line from the SN65DSI83 rather than polling the IRQ Status register. Delayed workqueue if the IRQ isn't wired up. If I read it right your log message is triggered by any bit being set in REG_IRQ_STAT. So an inconveniently timed correctable DSI error will set bit 4 and log the error even though it's been corrected. Likewise bit 7 / CHA_SYNCH_ERR could get triggered by an H or V sync packet being received in that 10-12ms window (we're in atomic_enable, so video is already running). If it's the PLL being unlocked that is the issue then it should only be checking bit 0. Or possibly reading the actual PLL lock status from REG_RC_LVDS_PLL_PLL_EN_STAT. Although as we've already checked that the PLL is locked via REG_RC_LVDS_PLL_PLL_EN_STAT earlier in the atomic_enable, I'm now a little confused as to the condition you are actually wanting to detect. Dave
