On Tue, 5 Apr 2022 at 14:08, Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> wrote: > > Hi Dave, > > On Tue, Apr 05, 2022 at 01:00:28PM +0100, Dave Stevenson wrote: > > On Tue, 5 Apr 2022 at 12:42, Laurent Pinchart wrote: > > > On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote: > > > > In rare cases, the bridge may not start up correctly, which usually > > > > leads to no display output. In case this happens, warn about it in > > > > the kernel log. > > > > > > Do you know what this is caused by ? It's a bit annoying to add a 10+ms > > > delay at start time just to be notified of rare cases. > > > > The datasheet [1] section 7.4.2 Initialization Sequence states in step 2 > > "After power is applied and stable, the DSI CLK lanes MUST be in HS > > state and the DSI data lanes MUST be driven > > to LP11 state" > > Data lanes shouldn't go to HS until step 8 after the DSI83 has been configured. > > > > Configuration from the driver is being done from atomic_enable, > > therefore the data lanes are likely in HS mode and sending video, not > > LP11. > > > > Deviate from the specified initialisation sequence at your peril! > > > > The SN65DSI8[3|4|5] is one of the DSI devices that I'd been looking at > > with the DSI ordering patches [2] so that we could initialise it in > > the way specified in the datasheet. I've had no responses to v2 of > > those patches though. > > Sounds like I need to review that :-) It's still in my queue, I'll try > to push it to the top. > > Do you think this patch could then be reverted ? If we can initialise the DSI host before the bridge for the pre_enable, then all the configuration moves to the atomic_pre_enable and there should be no need to have the delay. I can't 100% guarantee that, but one of the folks on the Pi forums is using [1] which does that, and is reporting it working well. (He's also using the DSI85 to take 2 DSI links and drive 2 LVDS single link panels) Dave [1] https://github.com/6by9/linux/commits/rpi-5.15.y-sn65dsi8x > > [1] https://www.ti.com/lit/ds/symlink/sn65dsi83.pdf > > [2] https://patchwork.freedesktop.org/series/100252/#rev2 > > > > > > Signed-off-by: Marek Vasut <marex@xxxxxxx> > > > > Cc: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > > > > Cc: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > > > > Cc: Linus Walleij <linus.walleij@xxxxxxxxxx> > > > > Cc: Robert Foss <robert.foss@xxxxxxxxxx> > > > > Cc: Sam Ravnborg <sam@xxxxxxxxxxxx> > > > > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx > > > > --- > > > > drivers/gpu/drm/bridge/ti-sn65dsi83.c | 5 +++++ > > > > 1 file changed, 5 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > > > index 19daaddd29a41..1d7c154ea1d79 100644 > > > > --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > > > @@ -488,6 +488,11 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, > > > > /* Clear all errors that got asserted during initialization. */ > > > > regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); > > > > regmap_write(ctx->regmap, REG_IRQ_STAT, pval); > > > > + > > > > + usleep_range(10000, 12000); > > > > + regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); > > > > + if (pval) > > > > + dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); > > > > } > > > > > > > > static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, > > -- > Regards, > > Laurent Pinchart
