On Tue, 15 Feb 2022 17:52:26 +0100 Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > Introduce a fourcc code for a single-channel frame buffer format with two > darkness levels. This can be used for two-level dark-on-light displays. > > As the number of bits per pixel is less than eight, this relies on > proper block handling for the calculation of bits per pixel and pitch. > > Signed-off-by: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > --- > drivers/gpu/drm/drm_fourcc.c | 2 ++ > include/uapi/drm/drm_fourcc.h | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c > index c12e48ecb1ab8aad..d00ce5d8d1fb9dd3 100644 > --- a/drivers/gpu/drm/drm_fourcc.c > +++ b/drivers/gpu/drm/drm_fourcc.c > @@ -151,6 +151,8 @@ const struct drm_format_info *__drm_format_info(u32 format) > { .format = DRM_FORMAT_C4, .depth = 4, .num_planes = 1, > .char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1, }, .hsub = 1, .vsub = 1 }, > { .format = DRM_FORMAT_C8, .depth = 8, .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 }, > + { .format = DRM_FORMAT_D1, .depth = 1, .num_planes = 1, > + .char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1, }, .hsub = 1, .vsub = 1 }, > { .format = DRM_FORMAT_R1, .depth = 1, .num_planes = 1, > .char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1, }, .hsub = 1, .vsub = 1 }, > { .format = DRM_FORMAT_R2, .depth = 2, .num_planes = 1, > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index 8605a1acc6813e6c..c15c6efcc65e5827 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -104,6 +104,9 @@ extern "C" { > #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [3:0] C */ > #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ > > +/* 1 bpp Darkness */ > +#define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [0] D */ > + Hi Geert, the same comment here as for C1 and R1 formats, need to specify pixel ordering inside a byte. I think it would also be good to explain the rationale why C1 and R1 are not suitable for this case and we need yet another 1-bit format in the commit message. For posterity, of course. I roughly remember the discussions. I also wonder if anyone would actually use D1. Should it be added anyway? There is no rule that a pixel format must be used inside the kernel AFAIK, but is there even a prospective userspace wanting this? Exposing R1 and inverting bits while copying to hardware might be enough? Thanks, pq > /* 1 bpp Red */ > #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [0] R */ >
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