On Tue, Nov 9, 2021 at 11:36 AM Adam Ford <aford173@xxxxxxxxx> wrote: > > On Tue, Nov 9, 2021 at 11:34 AM Tim Harvey <tharvey@xxxxxxxxxxxxx> wrote: > > > > Add nodes for MIPI DSI and LCDIF on IMX8MM > > > > I'm currently working with a set of patches to convert drm/exynos > > to a bridge [1] and add IMX8MM support [2] in order to get IMX8MM DSI > > working for display with a Raspberry Pi DSI touchscreen compatible with > > a Toshiba TC358762 DSI bridge and Powertip PH800480T013-IDF02 > > touchscreen. > > > > I had this working on a 5.10 kernel with the old blk-ctl and > > power-domain drivers that didn't make it into mainline but my 5.15 > > series with blk-ctl backported from next hangs right after > > "[drm] Initialized mxsfb-drm 1.0.0 20160824 for 32e00000.lcdif on minor 0" > > so I assume I have a power-domain not getting enabled. > > > > Please let me know if you see an issue with the way I've configured > > power-domain or clocks here. > > > > Best Regards, > > > > Tim > > [1] https://patchwork.kernel.org/project/dri-devel/list/?series=347439&archive=both&state=* > > [2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=359775&archive=both&state=* > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 68 +++++++++++++++++++++++ > > 1 file changed, 68 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 208a0ed840f4..195dcbff7058 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -188,6 +188,12 @@ > > clock-output-names = "clk_ext4"; > > }; > > > > + mipi_phy: mipi-video-phy { > > + compatible = "fsl,imx8mm-mipi-video-phy"; > > + syscon = <&disp_blk_ctrl>; > > + #phy-cells = <1>; > > + }; > > + > > psci { > > compatible = "arm,psci-1.0"; > > method = "smc"; > > @@ -1068,6 +1074,68 @@ > > #size-cells = <1>; > > ranges = <0x32c00000 0x32c00000 0x400000>; > > > > + lcdif: lcdif@32e00000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; > > The compatible "imx6sx-lcdif" implies MXSFB_V6. FWICT, it is like > MXSFB_V4, but with overlays and those overlays have more registers > configured in the mxsfb_kms driver. Have you tried using imx28-lcdif > to see if it makes a difference? Adam, Yes, I see now a discussion regarding this [1]. Changing to 'imx28-lcdif' still hangs. [1] https://patchwork.kernel.org/project/dri-devel/patch/20210620224834.189411-1-marex@xxxxxxx/ > > > + reg = <0x32e00000 0x10000>; > > + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, > > + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, > > + <&clk IMX8MM_CLK_DISP_APB_ROOT>; > > + clock-names = "pix", "disp_axi", "axi"; > > + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, > > + <&clk IMX8MM_CLK_DISP_AXI>, > > + <&clk IMX8MM_CLK_DISP_APB>; > > + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, > > + <&clk IMX8MM_SYS_PLL2_1000M>, > > + <&clk IMX8MM_SYS_PLL1_800M>; > > + assigned-clock-rate = <594000000>, <500000000>, <200000000>; > > Just through visual inspection, it appears that the > IMX8MM_CLK_DISP_AXI and IMX8MM_CLK_DISP_APB clock-parents and rates > are already set in the pgc_dispmix, so I think it's safe to reduce > those lines to just assigning IMX8MM_CLK_LCDIF_PIXEL to the > IMX8MM_VIDEO_PLL1_OUT with the assigned-clock-rate set to 594000000. > Ok, that makes sense. Incidentally I added some debug prints in imx_pgc_power_{up,down} and find we hang at: imx_pgc_power_down mipi Best Regards, Tim
