Applied. Thanks! Alex On Tue, Sep 22, 2020 at 9:11 AM Bernard Zhao <bernard@xxxxxxxx> wrote: > > Change the comment typo: "programm" -> "program". > > Signed-off-by: Bernard Zhao <bernard@xxxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- > drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- > 8 files changed, 14 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > index 770025a5e500..7c46937c1c0e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > @@ -98,7 +98,7 @@ struct amdgpu_bo_list_entry; > #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) > #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) > > -/* How to programm VM fault handling */ > +/* How to program VM fault handling */ > #define AMDGPU_VM_FAULT_STOP_NEVER 0 > #define AMDGPU_VM_FAULT_STOP_FIRST 1 > #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > index 3cafba726587..b0c0c438fc93 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > @@ -348,7 +348,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev) > /* Set the write pointer delay */ > WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); > > - /* programm the 4GB memory segment for rptr and ring buffer */ > + /* program the 4GB memory segment for rptr and ring buffer */ > WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | > (0x7 << 16) | (0x1 << 31)); > > @@ -541,7 +541,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) > uint64_t addr; > uint32_t size; > > - /* programm the VCPU memory controller bits 0-27 */ > + /* program the VCPU memory controller bits 0-27 */ > addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; > size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; > WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > index a566ff926e90..6e57001f6d0a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > @@ -253,7 +253,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) > uint64_t offset; > uint32_t size; > > - /* programm memory controller bits 0-27 */ > + /* program memory controller bits 0-27 */ > WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, > lower_32_bits(adev->uvd.inst->gpu_addr)); > WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, > @@ -404,7 +404,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev) > /* set the wb address */ > WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); > > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index 0a880bc101b8..d2d90fe5c6f8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -583,7 +583,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) > uint64_t offset; > uint32_t size; > > - /* programm memory controller bits 0-27 */ > + /* program memory controller bits 0-27 */ > WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, > lower_32_bits(adev->uvd.inst->gpu_addr)); > WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, > @@ -825,7 +825,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) > /* set the wb address */ > WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); > > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > index e07e3fae99b5..b44c8677ce8d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > @@ -1073,7 +1073,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) > WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, > (upper_32_bits(ring->gpu_addr) >> 2)); > > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index 927c330fad21..73699eafb51e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -910,7 +910,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, > (upper_32_bits(ring->gpu_addr) >> 2)); > > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > @@ -1068,7 +1068,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, > (upper_32_bits(ring->gpu_addr) >> 2)); > > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > index 23a9eb5b2c8a..e5d29dee0c88 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > @@ -900,7 +900,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, > (upper_32_bits(ring->gpu_addr) >> 2)); > > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > @@ -1060,7 +1060,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev) > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); > > fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > index e99bef6e2354..aa6f66c31709 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > @@ -887,7 +887,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo > WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, > (upper_32_bits(ring->gpu_addr) >> 2)); > > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > @@ -1067,7 +1067,7 @@ static int vcn_v2_5_start(struct amdgpu_device *adev) > WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); > > fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; > - /* programm the RB_BASE for ring buffer */ > + /* program the RB_BASE for ring buffer */ > WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > lower_32_bits(ring->gpu_addr)); > WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > -- > 2.28.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
