> -----Original Message-----
> From: Daniel Vetter <daniel@xxxxxxxx>
> Sent: Friday, May 8, 2020 1:13 PM
> To: Kahola, Mika <mika.kahola@xxxxxxxxx>
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx; daniel@xxxxxxxx
> Subject: Re: [PATCH v2] uapi/drm/drm_fourcc.h: Note on platform specificity
> for format modifiers
>
> On Fri, May 08, 2020 at 08:56:28AM +0200, Daniel Vetter wrote:
> > On Wed, May 06, 2020 at 03:08:27PM +0300, Mika Kahola wrote:
> > > Make an additional note on DRM format modifiers for x and y tiling.
> > > These format modifiers are defined for BDW+ platforms and therefore
> > > definition is not valid for older gens. This is due to address
> > > swizzling for tiled surfaces is no longer used. For newer platforms
> > > main memory controller has a more effective address swizzling algorithm.
> > >
> > > v2: Rephrase comment (Daniel)
> > >
> > > Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> >
> > Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
>
> Ok I assumed you'd just push that to drm-intel with commit rights or something,
> but that got stuck so applying to drm-misc-next now.
Ok. Thanks a lot!
Cheers,
Mika
>
> Cheers, Daniel
> >
> > > ---
> > > include/uapi/drm/drm_fourcc.h | 18 ++++++++++++------
> > > 1 file changed, 12 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > b/include/uapi/drm/drm_fourcc.h index 8bc0b31597d8..9e488d10f8b4
> > > 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -354,9 +354,12 @@ extern "C" {
> > > * a platform-dependent stride. On top of that the memory can apply
> > > * platform-depending swizzling of some higher address bits into bit6.
> > > *
> > > - * This format is highly platforms specific and not useful for
> > > cross-driver
> > > - * sharing. It exists since on a given platform it does uniquely
> > > identify the
> > > - * layout in a simple way for i915-specific userspace.
> > > + * Note that this layout is only accurate on intel gen 8+ or valleyview
> chipsets.
> > > + * On earlier platforms the is highly platforms specific and not
> > > + useful for
> > > + * cross-driver sharing. It exists since on a given platform it
> > > + does uniquely
> > > + * identify the layout in a simple way for i915-specific userspace,
> > > + which
> > > + * facilitated conversion of userspace to modifiers. Additionally
> > > + the exact
> > > + * format on some really old platforms is not known.
> > > */
> > > #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
> > >
> > > @@ -369,9 +372,12 @@ extern "C" {
> > > * memory can apply platform-depending swizzling of some higher address
> bits
> > > * into bit6.
> > > *
> > > - * This format is highly platforms specific and not useful for
> > > cross-driver
> > > - * sharing. It exists since on a given platform it does uniquely
> > > identify the
> > > - * layout in a simple way for i915-specific userspace.
> > > + * Note that this layout is only accurate on intel gen 8+ or valleyview
> chipsets.
> > > + * On earlier platforms the is highly platforms specific and not
> > > + useful for
> > > + * cross-driver sharing. It exists since on a given platform it
> > > + does uniquely
> > > + * identify the layout in a simple way for i915-specific userspace,
> > > + which
> > > + * facilitated conversion of userspace to modifiers. Additionally
> > > + the exact
> > > + * format on some really old platforms is not known.
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
> > >
> > > --
> > > 2.20.1
> > >
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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