Dne ponedeljek, 13. april 2020 ob 16:12:39 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Apr 13, 2020 at 6:11 PM Chen-Yu Tsai <wens@xxxxxxxx> wrote:
> > On Mon, Apr 13, 2020 at 5:55 PM Jernej Skrabec <jernej.skrabec@xxxxxxxx>
wrote:
> > > m divider in DDC clock register is 4 bits wide. Fix that.
> > >
> > > Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@xxxxxxxx>
> >
> > Reviewed-by: Chen-Yu Tsai <wens@xxxxxxxx>
>
> Cc stable?
I don't think it's necessary:
1. It doesn't change much (anything?) for me when reading EDID. I don't think
it's super important to have precise DDC clock in order to properly read EDID.
2. No matter if it has "Cc stable" tag or not, it will be eventually picked
for stable due to fixes tag.
This was only small observation when I was researching EDID readout issue on
A20 board, but sadly, I wasn't able to figure out why reading it sometimes
fails. I noticed similar issue on SoCs with DE2 (most prominently on OrangePi
PC2 - H5), but there was easy workaround - I just disabled video driver in U-
Boot. However, if A20 display driver gets disabled in U-Boot, it totally
breaks video output on my TV when Linux boots (no output). I guess there is
more fundamental problem with clocks than just field size. I think we should
add more constraints in clock driver, like preset some clock parents and not
allow to change parents when setting rate, but carefully, so simplefb doesn't
break. Such constraints should also solve problems with dual head setups.
Best regards,
Jernej
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