On Thu, Jan 09, 2020 at 05:30:05PM +0100, Mario Kleiner wrote: > On Thu, Jan 9, 2020 at 4:38 PM Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > wrote: > > > On Thu, Jan 09, 2020 at 05:26:57PM +0200, Ville Syrjälä wrote: > > > On Thu, Jan 09, 2020 at 04:07:52PM +0100, Mario Kleiner wrote: > > > > The panel reports 10 bpc color depth in its EDID, and the UEFI > > > > firmware chooses link settings at boot which support enough > > > > bandwidth for 10 bpc (324000 kbit/sec to be precise), but the > > > > DP_MAX_LINK_RATE dpcd register only reports 2.7 Gbps as possible, > > > > Does it actually or do we just ignore the fact that it reports 3.24Gbps? > > > > If it really reports 3.24 then we should be able to just add that to > > dp_rates[] in intel_dp_set_sink_rates() and be done with it. > > > > Although we'd likely want to skip 3.24 unless it really is reported > > as the max so as to not use that non-standard rate on other displays. > > So would require a bit fancier logic for that. > > > > > Was also my initial thought, but the DP_MAX_LINK_RATE reg reports 2.7 Gbps > as maximum. So dpcd[0x1] == 0xa ? What about the magic second version of DP_MAX_LINK_RATE at 0x2201 ? Hmm. I guess we should already be reading that via intel_dp_extended_receiver_capabilities(). -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
