Neil Armstrong <narmstrong@xxxxxxxxxxxx> writes: > The VPU embeds a "Register DMA" that can write a sequence of registers > on the VPU AHB bus, either manually or triggered by an internal IRQ > event like VSYNC or a line input counter. > > The initial implementation handles a single channel (over 8), triggered > by the VSYNC irq and does not handle the RDMA irq. > > The RDMA will be usefull to reset and program the AFBC decoder unit > on each vsync without involving the interrupt handler that can > be masked for a long period of time, producing display glitches. > > For this we use the meson_rdma_writel_sync() which adds the register > write tuple (VPU register offset and register value) to the RDMA buffer > and write the value to the HW. > > When enabled, the RDMA is enabled to rewritte the same sequence at the > next VSYNC event, until a new buffer is committed to the OSD plane. > > The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder > doesn't need a reset/reprogram at each vsync. > > Changes since v1 at [1]: > - Fixed a regression when AFBC was not used, adding a reset() call for the afbc module > - Added a define for the RDMA descriptor size > - Fixed overflow detection Reviewed-by: Kevin Hilman <khilman@xxxxxxxxxxxx> _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
