On 03/30/2012 02:24 PM, Chris Wilson wrote: > On Fri, 30 Mar 2012 14:11:47 +0200, Jiri Slaby <jslaby@xxxxxxx> wrote: >> On 03/30/2012 12:45 PM, Chris Wilson wrote: >>> On Fri, 30 Mar 2012 11:59:28 +0200, Jiri Slaby <jslaby@xxxxxxx> wrote: >>>> I don't know what to dump more, because iir is obviously zero too. What >>>> other sources of interrupts are on the (G33) chip? >>> >>> IIR is the master interrupt, with chained secondary interrupt statuses. >>> If IIR is 0, the interrupt wasn't raised by the GPU. >> >> This does not make sense, the handler does something different. Even if >> IIR is 0, it still takes a look at pipe stats. > > That was introduced in 05eff845a28499762075d3a72e238a31f4d2407c to close > a race where the pipestat triggered an interrupt after we processed the > secondary registers and before reseting the primary. > > But the basic premise that we should only enter the interrupt handler > with IIR!=0 holds (presuming non-shared interrupt lines such as MSI). Ok, this behavior is definitely new. I get several "nobody cared" about this interrupt a week. This never used to happen. And something weird emerges in /proc/interrupts when this happens: 42: 1003292 1212890 PCI-MSI-edge �s����:0000:00:02.0 instead of 42: 1006715 1218472 PCI-MSI-edge i915@pci:0000:00:02.0 It very looks like the generic IRQ handling code is broken. Like it frees/corrupts irq_desc and then as well calls random handlers. Suspend/resume cycle helps in this case and "i915@pci:0000:00:02.0" is back in /proc/interrupts as can be seen above. Running 3.3.0-next-20120326_64+ now. thanks, -- js suse labs _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
