On Fri, 30 Mar 2012 14:11:47 +0200, Jiri Slaby <jslaby@xxxxxxx> wrote: > On 03/30/2012 12:45 PM, Chris Wilson wrote: > > On Fri, 30 Mar 2012 11:59:28 +0200, Jiri Slaby <jslaby@xxxxxxx> wrote: > >> I don't know what to dump more, because iir is obviously zero too. What > >> other sources of interrupts are on the (G33) chip? > > > > IIR is the master interrupt, with chained secondary interrupt statuses. > > If IIR is 0, the interrupt wasn't raised by the GPU. > > This does not make sense, the handler does something different. Even if > IIR is 0, it still takes a look at pipe stats. That was introduced in 05eff845a28499762075d3a72e238a31f4d2407c to close a race where the pipestat triggered an interrupt after we processed the secondary registers and before reseting the primary. But the basic premise that we should only enter the interrupt handler with IIR!=0 holds (presuming non-shared interrupt lines such as MSI). -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
