On 03/30/2012 12:45 PM, Chris Wilson wrote: > On Fri, 30 Mar 2012 11:59:28 +0200, Jiri Slaby <jslaby@xxxxxxx> wrote: >> I don't know what to dump more, because iir is obviously zero too. What >> other sources of interrupts are on the (G33) chip? > > IIR is the master interrupt, with chained secondary interrupt statuses. > If IIR is 0, the interrupt wasn't raised by the GPU. This does not make sense, the handler does something different. Even if IIR is 0, it still takes a look at pipe stats. And this is MSI, so there can be no other source of the interrupt. (Except broken IRQ routing.) I may try to boot with MSIs off if you think it's important. thanks, -- js suse labs _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
