At Mon, 23 Aug 2010 14:19:22 +0800,
Zhenyu Wang wrote:
>
> On 2010.08.23 08:02:42 +0200, Takashi Iwai wrote:
> >
> > Also, I don't understand the logic of 40bit addr calculation:
> >
> > > static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
> > > dma_addr_t addr, int type)
> > > {
> > > /* Shift high bits down */
> > > addr |= (addr >> 28) & 0xff;
> >
> > Isn't it 0xff0?
> >
>
> No. This depends on hw 32bit PTE format for sandybridge.
>
> bit 31 bit 11 bit 4 bit 0
> |<-physical addr 31:12->|<-physical addr 39:32->|<-cache ctl 3:1->|valid|
Then I really don't understand why it works.
You shift 28bit and mask with 0xff. Obviously it overwrite bits 0:3
with original 28:31 bits. Masking 0xff0 fixes the issue.
And, the information like above would be greatly helpful if put into
either changelog or comment...
thanks,
Takashi
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