On 2010.08.23 08:31:42 +0200, Takashi Iwai wrote:
> > bit 31 bit 11 bit 4 bit 0
> > |<-physical addr 31:12->|<-physical addr 39:32->|<-cache ctl 3:1->|valid|
>
> Then I really don't understand why it works.
> You shift 28bit and mask with 0xff. Obviously it overwrite bits 0:3
> with original 28:31 bits. Masking 0xff0 fixes the issue.
>
ah, sorry, my stupid. Thanks for catching this!
Subject: [PATCH] agp/intel: fix physical address mask bits for sandybridge
It should shift bit 39-32 into pte's bit 11-4.
Reported-by: Takashi Iwai <tiwai@xxxxxxx>
Signed-off-by: Zhenyu Wang <zhenyuw@xxxxxxxxxxxxxxx>
---
drivers/char/agp/intel-gtt.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index d22ffb8..0edfc87 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1333,8 +1333,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
dma_addr_t addr, int type)
{
- /* Shift high bits down */
- addr |= (addr >> 28) & 0xff;
+ /* gen6 has bit11-4 for physical addr bit39-32 */
+ addr |= (addr >> 28) & 0xff0;
/* Type checking must be done elsewhere */
return addr | bridge->driver->masks[type].mask;
--
1.7.0.4
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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