Hi Russell, On Sat, Jun 22, 2019 at 5:27 PM Russell King - ARM Linux admin <linux@xxxxxxxxxxxxxxx> wrote: > > On Sat, Jun 22, 2019 at 08:26:53PM +0100, Russell King - ARM Linux admin wrote: > > Well, this doesn't appear to completely solve the problem either - > > one out of four of my platforms still spat out the error (because > > the SDMA initialisation can run on a different CPU to that which > > receives the interrupt.) > > > > I've thought about using a completion, but that doesn't work either, > > because in the case of a single CPU, the interrupts will be masked, > > so we can't wait for completion. I think we need to eliminate that > > spinlock around this code. > > It looks like iMX6 Dual does not initialise DMA properly using the 1.1 > firmware - md5sum is: > > 5d4584134cc4cba62e1be2f382cd6f3a /lib/firmware/imx/sdma/sdma-imx6q.bin > > I've tried extending the timeout to 5ms, checking HI[0] (both from the > interrupt handler and from sdma_run_channel0() to cover the case of a > single-core setup). > > After boot: > > 60: 0 0 GPC 2 Level sdma > > So no interrupt was received. Looking at the registers: > > # /shared/bin32/devmem2 0x20ec02c > Value at address 0x020ec02c: 0x00000000 <= H_INTRMASK > # /shared/bin32/devmem2 0x20ec004 > Value at address 0x020ec004: 0x00000000 <= H_INTR > # /shared/bin32/devmem2 0x20ec00c > Value at address 0x020ec00c: 0x00000000 <= H_START > # /shared/bin32/devmem2 0x20ec008 > Value at address 0x020ec008: 0x00000001 <= H_STATSTOP > > Any ideas? Could you please try this patch from Robin? http://lists.infradead.org/pipermail/linux-arm-kernel/2019-June/661914.html Thanks
