On Wed, Jan 11, 2017 at 05:18:10PM +0200, Andy Shevchenko wrote:
> The integrated DMA (iDMA 32-bit) is Intel designed DMA controller which mimics
> Synopsys Designware DMA. This patch appends the register mappings for the parts
> which are slightly different to the DesignWare hardware.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> ---
> drivers/dma/dw/regs.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 53 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
> index ba26d6bce06d..85752237ebbb 100644
> --- a/drivers/dma/dw/regs.h
> +++ b/drivers/dma/dw/regs.h
> @@ -3,6 +3,7 @@
> *
> * Copyright (C) 2005-2007 Atmel Corporation
> * Copyright (C) 2010-2011 ST Microelectronics
> + * Copyright (C) 2016 Intel Corporation
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License version 2 as
> @@ -13,6 +14,8 @@
> #include <linux/interrupt.h>
> #include <linux/dmaengine.h>
>
> +#include <linux/io-64-nonatomic-hi-lo.h>
> +
> #include "internal.h"
>
> #define DW_DMA_MAX_NR_REQUESTS 16
> @@ -86,9 +89,9 @@ struct dw_dma_regs {
> DW_REG(ID);
> DW_REG(TEST);
>
> - /* reserved */
> - DW_REG(__reserved0);
> - DW_REG(__reserved1);
> + /* iDMA 32-bit support */
> + DW_REG(CLASS_PRIORITY0);
> + DW_REG(CLASS_PRIORITY1);
>
> /* optional encoded params, 0x3c8..0x3f7 */
> u32 __reserved;
> @@ -100,6 +103,17 @@ struct dw_dma_regs {
>
> /* top-level parameters */
> u32 DW_PARAMS;
> +
> + /* component ID */
> + u32 COMP_TYPE;
> + u32 COMP_VERSION;
> +
> + /* iDMA 32-bit support */
> + DW_REG(FIFO_PARTITION0);
> + DW_REG(FIFO_PARTITION1);
> +
> + DW_REG(SAI_ERR);
> + DW_REG(GLOBAL_CFG);
> };
>
> /*
> @@ -216,6 +230,37 @@ enum dw_dma_msize {
> /* Bitfields in CFG */
> #define DW_CFG_DMA_EN (1 << 0)
>
> +/* iDMA 32-bit support */
> +
> +/* Bitfields in CTL_HI */
> +#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
> +#define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
> +#define IDMA32C_CTLH_DONE (1 << 17)
> +#define IDMA32C_CTLH_CH_WEIGHT_MASK GENMASK(28, 18) /* weight mask */
> +#define IDMA32C_CTLH_CH_WEIGHT(x) ((x) << 18) /* weight */
> +#define IDMA32C_CTLH_CH_CLASS_MASK GENMASK(31, 29) /* priority class mask */
> +#define IDMA32C_CTLH_CH_CLASS(x) ((x) << 29) /* priority class */
Are we planning to support weights?
--
~Vinod
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