The series add a support of Intel integrated DMA (iDMA 32-bit) hardware to dw_dmac driver. The series has been tested on Intel Merrifield with SPI attached TFT displays at their maximum speed (25MHz and 10MHz). Since v2: - remove update of users of this IP (Vinod) - comment, introduced in patch 3, is left untouched in patch 7 because there are no limitations for iDMA 32-bit. Since v1: - rebase on top of v4.10-rc2 - incorporate Jarkko's fix for unaligned data as patch 1 - use channel drain only when terminate transfer - fix bytes2block() implementation - tested with TFT SPI displays at their maximum speed (25MHz and 10MHz) Andy Shevchenko (7): dmaengine: dw: register IRQ and DMA pool with instance ID dmaengine: dw: replace convert_burst() with one liner dmaengine: dw: extract dwc_chan_pause() for future use dmaengine: dw: introduce block2bytes() and bytes2block() dmaengine: dw: introduce register mappings for iDMA 32-bit dmaengine: dw: add support of iDMA 32-bit hardware dmaengine: dw: we do support Merrifield SoC in PCI mode Jarkko Nikula (1): dmaengine: dw: Fix data corruption in large device to memory transfers drivers/dma/dw/core.c | 204 ++++++++++++++++++++++++----------- drivers/dma/dw/pci.c | 16 +++ drivers/dma/dw/platform.c | 1 + drivers/dma/dw/regs.h | 63 ++++++++++- include/linux/dma/dw.h | 2 + include/linux/platform_data/dma-dw.h | 2 + 6 files changed, 223 insertions(+), 65 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
