+AD4- On Fri, 2016-11-04 at 12:16 +-0000, Bharat Kumar Gogada wrote: +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- On Thu, Oct 27, 2016 at 02:31:08PM +-0000, Bharat Kumar Gogada wrote: +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- On Thu, Oct 27, 2016 at 12:57:08PM +-0000, Bharat Kumar Gogada +AD4- +AD4- +AD4- +AD4- +AD4- wrote: +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- Hi All, +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- We have a PCIe end point with DMA controller in it. +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- We are planning to code using DMA frame work for this DMA +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- controller. +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- The PCIe End Point can be used on both ARM64 and x86 +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- platforms. +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- We are planning to develop dmaengine driver and client driver +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- model. +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- In ARM64 case dmaengine driver and client driver are probed +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- using device tree and also channel information is also +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- obtained from device tree. +AD4- +AD4- +AD4- +AD4- +AD4- I think more details are necessary here. +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- Why is +ACo-anything+ACo- necessary in the DT if this is contained +AD4- +AD4- +AD4- +AD4- +AD4- within a +AD4- +AD4- +AD4- +AD4- +AD4- (probeable) PCIe endpoint? +AD4- +AD4- +AD4- +AD4- Thanks Mark. +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- Yes as you said it is PCIe probeable device, sorry I missed some +AD4- +AD4- +AD4- +AD4- information, in +AD4- +AD4- +AD4- case of ARM64 +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- if we invoke client driver from device tree where we can pass +AD4- +AD4- +AD4- +AD4- channel +AD4- +AD4- +AD4- information +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- such as number of channels, direction and other things.+AKAAoA-So in +AD4- +AD4- +AD4- +AD4- this case how +AD4- +AD4- +AD4- will client driver request +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- the channel it want to use, to dmaengine driver ? +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- In case of x86 on what basis client driver can be probed and +AD4- +AD4- +AD4- +AD4- request the dma +AD4- +AD4- +AD4- channels, if we already use +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- Vendor and device id for dmaengine driver ? +AD4- +AD4- +AD4- ACPI what else.. +AD4- +AD4- +AD4- +AD4- +AD4- +AD4- You can the request lines in client ACPI data and it can use to +AD4- +AD4- +AD4- filter the request. There are already dmaengine drivers which use +AD4- +AD4- +AD4- ACPI, so please check the source.. +AD4- +AD4- +AD4- +AD4- +AD4- Thanks vinod. +AD4- +AD4- +AD4- +AD4- We have+AKAAoA-a scenario where DMA client driver needs to access PCI bars +AD4- +AD4- of end point, but the DMA core driver is the one which has access to +AD4- +AD4- pcie resources. Is there any way we can pass this bar information to +AD4- +AD4- client driver through DMA framework ? +AD4- +AD4- Is the BAR a dma transaction address (src/dstn) or a resource for the DMA +AD4- controller? +AD4- It is end point specific logic that is mapped to other bars (One bar will be as dma resource), these can be IP specific registers like statistics, so how can the client driver have access these resources ? Thanks +ACY- Regards, Bharat -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
