On Wed, 2016-04-13 at 17:48 +0300, Andy Shevchenko wrote: > Wait, you mean flow control between DMA controller and UART FIFO, or > I > misread you? Yup. It's a while since I read the spec and talked to the relevant people but... I have this memory that the FIFO fill signal and DMA block were 'wired up' @ the AHB level. That would be how the UART and DMA block would flow-control each other for descriptor chaining at any rate and so one assumes that its active at the block-to-fifo layer. Meh I don't have the UART EAS anymore to comment in detail.. I think the right thing to do is to be safe (so I'll ACK your series) and then run an experiment to push the burst size upwards. If you have the EAS handy though it might be worthwhile working out when the DMA block will flow-control w/r to the FIFO fill level - I *think* (but can't prove since I don't have the EAS anymore) that it's safe to push that value higher. --- bod -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
