On Wed, 2016-04-13 at 15:34 +0100, Bryan O'Donoghue wrote:
> On Wed, 2016-04-13 at 15:03 +0300, Andy Shevchenko wrote:
> >
> > Because a probability of FIFO overrun.
> >
> > There is a big chapter ("Peripheral Burst Transaction Requests") in
> > dw_apb_dmac_db.pdf covering this.
> I thought there was flow control between the controller and the FIFO
> here ? I don't have the spec SoC spec for the UART to hand but, if
> memory serves...
Wait, you mean flow control between DMA controller and UART FIFO, or I
misread you?
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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