On 02/24/2016 07:37 AM, Sekhar Nori wrote: > On Wednesday 24 February 2016 08:50 AM, Peter Hurley wrote: >> Just to follow-up on what Sebastian wrote. >> >> As he pointed out, these spurious interrupts are not timeout interrupts. >> Since IIR_UART[0] == 1, no uart interrupt is pending. >> >> As he wrote, these count as spurious interrupts and trigger >> interrupt shutdown at 100000 (unless acked as uart interrupts). > > Okay, by adding a printk to where the check for UART_IIR_NO_INT is in > omap_8250_dma_handle_irq(), I do see that UART irq handler is called > when there is apparently no interrupt. > > I don't see the error interrupt count in /proc/interrupts go up although > the code is returning IRQ_NONE when this happens. I initially thought > that must be because of the interrupt being IRQF_SHARED. But getting rid > of IRQF_SHARED still does not lead to error count going up. I need to > spend some more time to see what is going on. > >> These spurious interrupts very nearly correspond 1:1 (but not quite) >> with each dma submission. So, for example, one test run had: >> >> @3Mbaud line rate >> 195826 submits >> 195823 completions >> >> 195704 spurious interrupts (ie., interrupts with IIR_UART[0] == 1) >> 0 RLSI interrupts (no line errors) (IIR_UART == 0xc6) >> 2 RX timeout interrupts (IIR_UART == 0xcc), >> one during i/o test and one at the end of i/o test >> 6 RDI interrupts (IIR_UART == 0xc4) >> >> The spurious interrupts occur with nearly 1:1 correspondence at _all_ >> line rates. >> >> Presumbably, the 6 RDI interrupts are from too-slow submission of >> the next DMA and the uart rx fifo has reached rx trigger level already. >> [NOTE: we should at least be using ping-pong dma buffers for rx so that >> there is always a next DMA buffer when the current buffer is completed]. >> >> There is no documentation in any of the OMAP TRMs regarding RDI >> interrupts while in DMA mode. Some guidance from TI would be appreciated. > > UART interrupts triggering while UART_IIR_NO_INT is set is weird enough. > I will check around internally with hardware folks here. Getting an > answer might take time. But this is easily reproducible so I am > optimistic we will get an answer soon. Thanks. Also, after looking over the latest errata for am335x, I was surprised not to see an errata for our TX DMA workaround. Currently, to get memory-to-device DMA to start *on am335x only* requires writing the 1st byte to the UART fifo to trigger DMA, which is pretty odd. It's almost as if the TX DMA trigger is edge-triggered rather than level-triggered. Let me know if you need more info. Regards, Peter Hurley -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
