On Tue, 04 Feb 2025 14:40:03 +0200, Cristian Ciocaltea wrote:
> VOP2 support for RK3588 SoC is currently not capable to handle the full
> range of display modes advertised by the connected screens, e.g. it
> doesn't cope well with non-integer refresh rates like 59.94, 29.97,
> 23.98, etc.
>
> There are two HDMI PHYs available on RK3588, each providing a PLL that
> can be used by three out of the four VOP2 video ports as an alternative
> and more accurate pixel clock source. They are able to handle display
> modes up to 4K@60Hz, anything above that, e.g. the maximum supported
> 8K@60Hz resolution, is supposed to be handled by the system CRU.
>
> [...]
Applied, thanks!
[4/5] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
commit: d0f17738778c12be629ba77ff00c43c3e9eb8428
[5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
commit: eb4262203d7d85eb7b6f2696816db272e41f5464
Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>
