On Tue, 04 Feb 2025 14:40:03 +0200, Cristian Ciocaltea wrote:
> VOP2 support for RK3588 SoC is currently not capable to handle the full
> range of display modes advertised by the connected screens, e.g. it
> doesn't cope well with non-integer refresh rates like 59.94, 29.97,
> 23.98, etc.
>
> There are two HDMI PHYs available on RK3588, each providing a PLL that
> can be used by three out of the four VOP2 video ports as an alternative
> and more accurate pixel clock source. They are able to handle display
> modes up to 4K@60Hz, anything above that, e.g. the maximum supported
> 8K@60Hz resolution, is supposed to be handled by the system CRU.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: display: vop2: Add optional PLL clock properties
commit: 79982cbac896768c3860c241df2028c3e75f5a6b
[2/5] drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation
commit: 9f40d7a94427a503e303b2a2d8db227d615e32c1
[3/5] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0
commit: 2c1268e7aad0819f38e56134bbc2095fd95fde1b
Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>
