Add dtschema for the MDIO controller found in the RTL9300 SoCs. The
controller is slightly unusual in that direct MDIO communication is not
possible. We model the MDIO controller with the MDIO buses as child
nodes and the PHYs as children of the buses. Because we do need the
switch port number to actually communicate over the MDIO bus this needs
to be supplied via the "realtek,port" property.
Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
---
Notes:
Changes in v5:
- Add back reg property to mdio-controller node
- Make unit address in the node name required
- Andrew suggested perhaps doing away with the realtek,port property and
providing the overall mapping via an array of phandles. I've explored
this a little, it is doable but I'm not sure it actually makes things
any clearer when the portmap has gaps so I haven't made this change.
Changes in v4:
- Model the MDIO controller with the buses as child nodes. We still need
to deal with the switch port number so this is represented with the
"realtek,port" property which needs to be added to the MDIO bus
children (i.e. the PHYs)
- Because the above is quite a departure from earlier I've dropped the
r-by
Changes in v3:
- Add r-by from Connor
Changes in v2:
- None
.../bindings/net/realtek,rtl9301-mdio.yaml | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml
diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml
new file mode 100644
index 000000000000..80456dc791eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek RTL9300 MDIO Controller
+
+maintainers:
+ - Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - realtek,rtl9302b-mdio
+ - realtek,rtl9302c-mdio
+ - realtek,rtl9303-mdio
+ - const: realtek,rtl9301-mdio
+ - const: realtek,rtl9301-mdio
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ '^mdio-bus@[0-4]$':
+ $ref: mdio.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ required:
+ - reg
+
+ patternProperties:
+ '^ethernet-phy@[a-f0-9]+$':
+ type: object
+ $ref: ethernet-phy.yaml#
+
+ properties:
+ realtek,port:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The MDIO communication on the RTL9300 is abstracted by the switch. At
+ the software level communication uses the switch port to address the
+ PHY with the actual MDIO bus and address having been setup via the
+ parent mdio-bus and reg property.
+
+ unevaluatedProperties: false
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio-controller@ca00 {
+ compatible = "realtek,rtl9301-mdio";
+ reg = <0xca00 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio-bus@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ realtek,port = <0>;
+ };
+ };
+
+ mdio-bus@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ realtek,port = <8>;
+ };
+ };
+ };
--
2.48.1
