On 2025-01-28 10:58 AM, Rob Herring wrote: > On Tue, Jan 28, 2025 at 10:03 AM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: >> >> On Tue, Jan 28, 2025 at 4:17 AM Yixun Lan <dlan@xxxxxxxxxx> wrote: >> >>> [Rob] >>>> If Linux can't handle 1 node for N gpio_chip's, then that's a Linux >>>> problem. Maybe it can, IDK. >>> >>> I haven't seen somthing like this to register 1 node for multi gpio_chips.. >>> To gpio/pinctrl maintainer (Linus Walleij), do you have suggestion on this? >> >> For Linux we can call bgpio_init() three times and >> devm_gpiochip_add_data() three times on the result and if we use the >> approach with three cells (where the second is instance 0,1,2 and the >> last one the offset 0..31) then it will work all just the same I guess? >> >> foo-gpios <&gpio 2 7 GPIO_ACTIVE_LOW>; >> >> for offset 7 on block 2 for example. >> >> We need a custom xlate function I suppose. >> >> It just has not been done that way before, everybody just did >> 2-cell GPIOs. > > You can do either 3 cells or 2 cells splitting the 1st cell into > <bank><index>. I'm pretty sure we have some cases of the latter. There is also at least one example of 3-cell GPIOs: Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml It supports controllers with varying numbers of pins per bank and banks in each instance. Compared to the design described above, it shares a single gpio_chip across all banks in a controller instance. Regards, Samuel
