On Thu, Jan 23, 2025 at 11:30:42AM +0000, Yixun Lan wrote: > Hi Olof: > thanks for your reivew > > On 12:03 Wed 22 Jan , Olof Johansson wrote: > > Hi, > > > > On Tue, Jan 21, 2025 at 11:38:11AM +0800, Yixun Lan wrote: > > > The GPIO controller of K1 support basic functions as input/output, > > > all pins can be used as interrupt which route to one IRQ line, > > > trigger type can be select between rising edge, failing edge, or both. > > > There are four GPIO ports, each consisting of 32 pins. > > > > > > Signed-off-by: Yixun Lan <dlan@xxxxxxxxxx> > > > --- > > > .../devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 116 +++++++++++++++++++++ > > > 1 file changed, 116 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml > > > new file mode 100644 > > > index 0000000000000000000000000000000000000000..dd9459061aecfcba84e6a3c5052fbcddf6c61150 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml > > > @@ -0,0 +1,116 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/gpio/spacemit,k1-gpio.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: SpacemiT K1 GPIO controller > > > + > > > +maintainers: > > > + - Yixun Lan <dlan@xxxxxxxxxx> > > > + > > > +description: > > > + The controller's registers are organized as sets of eight 32-bit > > > + registers with each set of port controlling 32 pins. A single > > > + interrupt line is shared for all of the pins by the controller. > > > + Each port will be represented as child nodes with the generic > > > + GPIO-controller properties in this bindings file. > > > > There's only one interrupt line for all ports, but you have a binding that > > duplicates them for every set of ports. That seems overly complicated, > > doesn't it? They'd all bind the same handler, so there's no benefit in > > providing the flexibility,. > > > yes, all ports share same interrupt line, but each port has its own > irq related handling register, so it make sense to describe as per gpio irqchip > > also see comments below > > > > +properties: > > > + $nodename: > > > + pattern: "^gpio@[0-9a-f]+$" > > > + > > > + compatible: > > > + const: spacemit,k1-gpio > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + "#address-cells": > > > + const: 1 > > > + > > > + "#size-cells": > > > + const: 0 > > > + > > > +patternProperties: > > > + "^gpio-port@[0-9a-f]+$": > > > + type: object > > > + properties: > > > + compatible: > > > + const: spacemit,k1-gpio-port > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + gpio-controller: true > > > + > > > + "#gpio-cells": > > > + const: 2 > > > + > > > + gpio-ranges: true > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + interrupt-controller: true > > > + > > > + "#interrupt-cells": > > > + const: 2 > > > + description: > > > + The first cell is the GPIO number, the second should specify interrupt > > > + flag. The controller does not support level interrupts, so flags of > > > + IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW should not be used. > > > + Refer <dt-bindings/interrupt-controller/irq.h> for valid flags. > > > > Same here, since there's no real flexibility between the banks, it might > > make sense to consider a 3-cell GPIO specifier instead, and having > how to handle the fourth gpio port? I would like to have uniform driver for all ports > > > the first cell indicate bank. I could see this argument go in either > > direction, but I'm not sure I understand why to provide a gpio-controller > > per bank. > > > > IIUC, your suggestion here was same as the implementation of patch v3 of this driver[1], > while combining all four ports into one irqchip, which NACKed by maintainer[2]. > I tend to agree having a gpio-controller per bank provide more flexibility, > easy to leverage generic gpio framework, even each port can be disabled or enabled, > and IMO having shared irq handler isn't really a problem.. > > [1] https://lore.kernel.org/r/20241225-03-k1-gpio-v3-0-27bb7b441d62@xxxxxxxxxx > [2] https://lore.kernel.org/r/CACRpkdZPD2C2iPwOX_kW1Ug8jVkdHhhc7iFycHtzj5LQ0XWNgQ@xxxxxxxxxxxxxx > https://lore.kernel.org/r/CACRpkdYgGho=VQabonq4HccEiXBH2qM76K45oDaV1Jyi0xZ-YA@xxxxxxxxxxxxxx Hmm, I don't understand the reasoning there, but it's not my subsystem. It seems worse to me to misdescribe the hardware as separate blocks with a device-tree binding that no longer describes the actual hardware, but it's not up to me. Let's get the platform support merged, ignore my feedback here -- we need more SoCs supported upstream and this code is good enough to go in as-is. -Olof
