On 27/01/2025 10:31, Sricharan R wrote: > From: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx> > > The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. > The RCG and PLL have a separate register space from the GCC. > Also the L3 cache has a separate pll and needs to be scaled along > with the CPU. > > Co-developed-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx> > Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx> Considering that there were multiple conflicting patches coming from Qualcomm around IPQ SoCs and that we are in the merge window, I will skip this patch. I suspect this duplicates the other chip as well, but that's your task to sync up internally. Best regards, Krzysztof
