Thanks for your hints, Conor! On Mon, 2025-01-13 at 17:37 +0000, Conor Dooley wrote: > > What are your thoughts? > > > > arch/arm64/boot/dts/sophgo/sg2000.dtsi | 164 +++++++++++++++++++++++++ > > 1 file changed, 164 insertions(+) > > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi > > > > diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > > new file mode 100644 > > index 000000000000..96afd342bde5 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > > @@ -0,0 +1,164 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include "../../../../riscv/boot/dts/sophgo/cv18xx.dtsi" > > +#include "../../../../riscv/boot/dts/sophgo/cv181x.dtsi" > > FWIW, this can just be #include <riscv/sophgo/<whatever>, /should/ be a > symlink for that, as there is for arm64. At the very least, I did see a > patch adding that link in the past. Check out what the RZ/Five is doing > (that's the riscv renesas chip) for an example of how this already has > been done - I think it's doing what your "Alternatively I can..." > paragraph describes. That's exactly what I needed! -- Alexander Sverdlin.
