On Sun, Jan 12, 2025 at 01:55:05AM +0100, Alexander Sverdlin wrote:
> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
>
> ---
> Dear ARM, RISCV, DT maintainers, I'd like to ask your opinion on the
> below patch, which I plan as a base for ARM64 BSP for dual-arch (RISCV or
> ARM64) Cvitek SoC SG2000. The main motivation for ARM64 support is the
> ARCH support in the upstream gcc, which is not that mature for RISCV.
>
> I believe it's the first time we already have quite some base in the
> tree for a SoC, so it would be advantageous to re-use it and not
> duplicate the same SoC structures in two places, especially having
> in mind that Cvitek/Sophgo are still working on upstreaming and by
> far not all HW blocks are populated in the SoC DTs. They focus primarely
> on RISCV, so ARM64 would be dragging behind in this case if it would be
> forked.
>
> On the other hand, including SoC dtsi from RISCV into ARM64 poses
> some technical challenges by itself, obviously CPU cores have to be
> deleted, same is true for interrupt controller. And the interrupt
> numbers are of course difference for ARM GIC, so they have to be
> overwritten.
>
> Alternatively I can split existing .dtsi included below into their
> RISCV-specific and generic parts, so that both ARM64 and RISCV would
> include generic part and their corresponding ARCH-specific parts
> bringing CPU cores + interrupt controller + IRQ numbers for each and
> every device separately.
>
> The below example isactually booting (being included into board-level
> DT), so it's a real example I'd be ready to submit if there will be
> no objections of the cross-ARCH include approach in general.
>
> What are your thoughts?
>
> arch/arm64/boot/dts/sophgo/sg2000.dtsi | 164 +++++++++++++++++++++++++
> 1 file changed, 164 insertions(+)
> create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
>
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> new file mode 100644
> index 000000000000..96afd342bde5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> @@ -0,0 +1,164 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "../../../../riscv/boot/dts/sophgo/cv18xx.dtsi"
> +#include "../../../../riscv/boot/dts/sophgo/cv181x.dtsi"
> +
> +/delete-node/ &cpu0;
> +/delete-node/ &plic;
> +/delete-node/ &clint;
You can split the riscv specific device into a separate file
so you not need to set delete-node.
> +
> +/ {
> + compatible = "sophgo,sg2000";
> + interrupt-parent = <&gic>;
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>; /* 512MiB */
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + always-on;
> + clock-frequency = <25000000>;
> + };
> +
> + gic: interrupt-controller@1f01000 {
> + compatible = "arm,cortex-a15-gic";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x01f01000 0x1000>,
> + <0x01f02000 0x2000>;
> + };
> +
> + soc {
> + /delete-property/ interrupt-parent;
> +
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,sg2000-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> + };
> +};
> +
> +&cpus {
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache {
> + compatible = "cache";
> + };
> +};
> +
> +&clk {
> + compatible = "sophgo,sg2000-clk";
> +};
> +
> +&saradc {
> + interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
> +};
> +
> +&dmac {
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&spi0 {
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&spi1 {
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&spi2 {
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&spi3 {
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&uart0 {
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&uart1 {
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&uart2 {
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&uart3 {
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&uart4 {
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&porta {
> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&portb {
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&portc {
> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&portd {
> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c0 {
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c1 {
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c2 {
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c3 {
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c4 {
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&emmc {
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&sdhci0 {
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&sdhci1 {
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +};
>
> --
> Alexander Sverdlin.
>
