Hi Jonathan, On Sat, Jan 4, 2025 at 2:59 PM Jonathan Cameron <jic23@xxxxxxxxxx> wrote: > > On Tue, 31 Dec 2024 20:42:07 +0100 > Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> wrote: > > > The SARADC IP on the GXLX SoC itself is identical to the one found on > > GXL SoCs. However, GXLX SoCs require poking the first three bits in the > > MESON_SAR_ADC_REG12 register to get the three MPLL clocks (used as clock > > generators for the audio frequencies) to work. > > > > The reason why there are MPLL clock bits in the ADC register space is > > entirely unknown and it seems that nobody is able to comment on this. > > So clearly mark this as a workaround and add a warning so users are > > notified that this workaround can change (once we know what these bits > > actually do). > > So IIUC this is to make some non ADC component work. That's correct > How are you handling dependencies? The ADC driver might not be loaded or > is there some reason it definitely is at the point where the audio driver > loads? Unfortunately there are no dependencies at the moment. To me it's not even 100% clear if those bits are a dependency for the audio IP or if they are instead linked with the clock controller (more background info: some of the MPLL clocks are - at least in theory, in practice we don't use that - are also used as input for the Mali GPU and video subsystem. The only practical usage that I'm aware of is the audio controller). Christian and I have both tried with all of our contacts at Amlogic but did not get any answers. If I knew the purpose of these bits I'd model them as whatever they are (resets, clock gates, ...) and provide proper dt-bindings. Best regards, Martin
