Hello, Amlogic GXLX SoCs seem to be mostly the same silicon as GXL. The only known differences are: - one less Mali-450 GPU core - no VP9 codec - and an odd one: the three MPLL clocks need a bit toggled in the SAR ADC register space This series attempt to fix audio output (which relies on the MPLL clocks) on the GXLX boards. Unfortunately all we have is a downstream commit [0] without any further explanation (or anyone who wants to provide details on this). Since it's not clear if this is a gate, a reset or some other hardware fix: the driver side includes a warning for users to update their .dtb along with kernel images in case we ever figure out what these bits do and how to model them properly. [0] https://github.com/khadas/linux/commit/d1d98f2ed8c83eb42af8880ed8e206aa402dd70a#diff-c5aaf54323ef93777c5083de37f933058ea8d0af79a1941e0b5a0667dc0f89b3 Martin Blumenstingl (2): dt-bindings: iio: adc: amlogic,meson-saradc: Add GXLX SoC compatible iio: adc: meson: add support for the GXLX SoC .../iio/adc/amlogic,meson-saradc.yaml | 1 + drivers/iio/adc/meson_saradc.c | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+) -- 2.47.1
