On Tue, Dec 10, 2024 at 05:11:05PM +0800, Xiangxu Yin wrote:
> Add DisplayPort controller and phy configuration for QCS615 platform.
>
> Signed-off-by: Xiangxu Yin <quic_xiangxuy@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 107 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 105 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 0a629c44e960e38891f48a8a021b86a6c1dadea1..dbd6eae267d7470d9b9a6c303eac03b64c3df3fc 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -17,6 +17,7 @@
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -2889,6 +2890,7 @@ ports {
> port@0 {
> reg = <0>;
> dpu_intf0_out: endpoint {
> + remote-endpoint = <&mdss_dp0_in>;
> };
> };
>
> @@ -3002,6 +3004,107 @@ mdss_dsi0_phy: phy@ae94400 {
>
> status = "disabled";
> };
> +
> + mdss_dp0: displayport-controller@ae90000 {
Which order should nodes follow in DT?
> + compatible = "qcom,sm6150-dp";
> +
> + reg = <0x0 0xae90000 0x0 0x200>,
> + <0x0 0xae90200 0x0 0x200>,
> + <0x0 0xae90400 0x0 0x600>,
> + <0x0 0xae90a00 0x0 0x600>;
0x0ae90000, etc. If it is not written in your company's "upstreaming"
document, please update it. If it is written there, why didn't you
follow it?
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <12>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <&mdss_dp_phy QMP_USB43DP_DP_LINK_CLK>,
> + <&mdss_dp_phy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <&mdss_dp_phy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_CX>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dp0_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdss_dp0_out: endpoint {
> + };
> + };
> + };
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> +
> + mdss_dp_phy: phy@88e9000 {
Also misplaced node.
> + compatible = "qcom,qcs615-qmp-dp-phy";
> +
> + reg = <0x0 0x88e9000 0x0 0x200>,
> + <0x0 0x88e9400 0x0 0x10c>,
> + <0x0 0x88e9800 0x0 0x10c>,
> + <0x0 0x88e9c00 0x0 0x200>;
0x088e9000, etc.
> +
> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
> + clock-names = "cfg_ahb",
> + "ref";
> + clock-output-names = "dp_phy_link_clk",
> + "dp_phy_vco_div_clk";
> +
> + resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
> + reset-names = "phy";
> +
> + qcom,tcsr-reg = <&tcsr 0xb24c>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + status = "disabled";
> + };
> };
>
> dispcc: clock-controller@af00000 {
> @@ -3013,8 +3116,8 @@ dispcc: clock-controller@af00000 {
> <&mdss_dsi0_phy 0>,
> <&mdss_dsi0_phy 1>,
> <0>,
> - <0>,
> - <0>;
> + <&mdss_dp_phy QMP_USB43DP_DP_LINK_CLK>,
> + <&mdss_dp_phy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> #clock-cells = <1>;
> #reset-cells = <1>;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
