From: Chen Wang <unicorn_wang@xxxxxxxxxxx> Add binding for Sophgo SG2042 MSI controller. Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx> --- .../sophgo,sg2042-msi.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml new file mode 100644 index 000000000000..0c9e9d07e5ae --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 MSI Controller + +maintainers: + - Chen Wang <unicorn_wang@xxxxxxxxxxx> + +description: + This interrupt controller is in Sophgo SG2042 for transforming interrupts from + PCIe MSI to PLIC interrupts. + +allOf: + - $ref: /schemas/interrupts.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: sophgo,sg2042-msi + + reg: + items: + - description: clear register + + reg-names: + items: + - const: clr + + msi-controller: true + + msi-ranges: + maxItems: 1 + + sophgo,msi-doorbell-addr: + description: + u64 value of the MSI doorbell address + $ref: /schemas/types.yaml#/definitions/uint64 + +required: + - compatible + - reg + - reg-names + - msi-controller + - msi-ranges + - sophgo,msi-doorbell-addr + +additionalProperties: true + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + msi: msi-controller@30000000 { + compatible = "sophgo,sg2042-msi"; + reg = <0x30000000 0x4>; + reg-names = "clr"; + msi-controller; + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; + sophgo,msi-doorbell-addr = <0x00000070 0x30010300>; + interrupt-parent = <&plic>; + }; -- 2.34.1
