From: Chen Wang <unicorn_wang@xxxxxxxxxxx>
This controller is on the Sophgo SG2042 SoC to transform interrupts from
PCIe MSI to PLIC interrupts.
Thanks,
Chen
---
Changes in v2:
The patch series is based on v6.13-rc2.
Fixed following issues as per comments from Rob Herring, Thomas Gleixner, thanks.
- Improve driver binding description, use msi-ranges instread.
- Improve driver code:
- Improve coding style.
- Fixed bug that possible memory leak of bitmap when sg2042_msi_init_domains returns error.
- Use guard(mutex).
- Use the MSI parent model.
Changes in v1:
The patch series is based on v6.12-rc7. You can simply review or test the
patches at the link [1].
Link: https://lore.kernel.org/linux-riscv/cover.1731296803.git.unicorn_wang@xxxxxxxxxxx/ [1]
---
Chen Wang (3):
dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI
irqchip: Add the Sophgo SG2042 MSI interrupt controller
riscv: sophgo: dts: add msi controller for SG2042
.../sophgo,sg2042-msi.yaml | 63 ++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 10 +
drivers/irqchip/Kconfig | 12 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-sg2042-msi.c | 285 ++++++++++++++++++
5 files changed, 371 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml
create mode 100644 drivers/irqchip/irq-sg2042-msi.c
base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4
--
2.34.1
