On 12/5/24 12:22 PM, David Lechner wrote:
> On 12/3/24 3:15 AM, Eason Yang wrote:
>> +static int nct720x_read_raw(struct iio_dev *indio_dev,
>> + struct iio_chan_spec const *chan,
>> + int *val, int *val2, long mask)
>> +{
>> + int index = nct720x_chan_to_index[chan->address];
>> + u16 volt;
>> + unsigned int value;
>> + int err;
>> + struct nct720x_chip_info *chip = iio_priv(indio_dev);
>> +
>> + if (chan->type != IIO_VOLTAGE)
>> + return -EOPNOTSUPP;
>> +
>> + guard(mutex)(&chip->access_lock);
>> + switch (mask) {
>> + case IIO_CHAN_INFO_RAW:
>> + err = regmap_read(chip->regmap16, REG_VIN[index], &value);
>> + if (err < 0)
>> + return err;
>> + volt = (u16)value;
>> + *val = volt >> 3;
>
> It seems strange that this is 13 bits when the chips are 8 and 12 bit.
>
>> + return IIO_VAL_INT;
>> + case IIO_CHAN_INFO_SCALE:
>> + /* From the datasheet, we have to multiply by 0.0004995 */
>
> The scale is the same for both 8 bit and 12 bit chips?
>
>> + *val = 0;
>> + *val2 = 499500;
>> + return IIO_VAL_INT_PLUS_NANO;
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
Sorry, I got confused. The difference between the two chips is the
number of channels, not the number of bits. Please ignore these two
comments.
