On Mon, Nov 18, 2024 at 04:26:19PM +0800, Ziyue Zhang wrote: > From: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> > > Add configurations in devicetree for PCIe0, including registers, clocks, > interrupts and phy setting sequence. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> > --- > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 ++++++ > arch/arm64/boot/dts/qcom/qcs615.dtsi | 158 +++++++++++++++++++++++ > 2 files changed, 200 insertions(+) Split into platform and SoC changes. -- With best wishes Dmitry
