On Thu, Oct 24, 2024 at 02:35:37PM +0200, Nuno Sá wrote: > On Wed, 2024-10-23 at 17:30 +0100, Conor Dooley wrote: > > On Wed, Oct 23, 2024 at 04:56:54PM +0200, Nuno Sa wrote: > > > In order to access the registers of the HW, we need to make sure that > > > the AXI bus clock is enabled. Hence let's increase the number of clocks > > > by one. > > > > > > In order to keep backward compatibility, the new axi clock must be the > > > last phandle in the array. To make the intent clear, a non mandatory > > > clock-names property is also being added. > > > > Hmm, I'm not sure. I think clock-names actually may need to be mandatory > > here, as otherwise you'll not what the second clock is. The driver would > > have to interpret no clock-names meaning clock 2 was clkin2. > > > > > > So the way things are now is that we just get the parents count with > of_clk_get_parent_count() and then get the names with of_clk_get_parent_name() and > this is given into 'struct clk_init_data'. So they are effectively clk_parents of the > clock we're registering and as you can see clock-names does not really matter. What > I'm trying to do is to keep this and still allow to get the AXI bus clock which is > something we should get and enable and not rely on others to do it. The idea is then > to add the axi bus clock as the last one in the clocks property and I will get it by > index with of_clk_get(). The rest pretty much remains the same and we just need to > decrement by one the number of parent clocks as the axi clock is not really a parent > of our output clock. I mean, if it works, and you can always disambiguate between whether or not someone has two clkins or one clkin and the axi clock, then Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
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